A conventional digital signal processor (DSP) may include a static random access memory (SRAM)-based embedded memory and a flip flop-based shift register. Therefore, in the conventional digital signal processor, the memory and the shift register may occupy a significant portion of area and consume a significant fraction of power. Accordingly, if the conventional digital signal processor is used in a smart phone or Internet-of-Thing (IoT) which is heavily constrained in power and area, this problem may be worsened.
Accordingly, in recent years, there have been actively studied digital signal processors using a non-volatile memory, such as a spin-transfer torque magnetic random-access memory (STT-RAM), domain wall memory, and a resistive random-access memory (ReRAM), instead of the static random access memory.
The non-volatile memory has the merits of high density, low power, and low cost. Therefore, if the non-volatile memory is used in a digital signal processor, it is efficient in reduction of area and cost for power. Further, the non-volatile memory has read and write speeds which are asymmetrical to each other.
The memory access of the digital signal processor is quite regular. Therefore, memory access patterns of the digital signal processor are predictable. Accordingly, a digital signal processor architecture for using sequential memory access and a non-volatile memory in which read and write operations are asymmetrical to each other is needed.
In this regard, Korean Patent Laid-open Publication No. 10-2014-0134515 (entitled “Digital signal processor and method for inputting and outputting data”) discloses a digital signal processor including: a DRAM including multiple memory cells configured to store data in a parasitic capacitor; and a core logic configured to perform data write, read, or update operations to the DRAM based on a preset digital signal processing algorithm, and a method for inputting and outputting data.